Integrated circuit devices, such as field programmable gate array (FPGA) devices and application specific integrated circuits (ASICs), may be used to transmit and receive high-speed signals using a contiguous multi-rate communications protocol. There are a variety of applications or input-output interfaces that require a contiguous multi-rate communications protocol. An example of such an interface includes a High Definition Multimedia Interface (HDMI) standard.
Generally, transceiver circuitry is adapted to operate at predetermined or specific data rates. A contiguous multi-rate protocol, such as the HDMI standard, on the other hand, allows any arbitrary clock rate. For example, in the HDMI standard, the pixel clock rate can range from 25 megahertz (MHz) to 600 MHz with associated line rates ranging from 250 megabits per second (Mbps) to 6 gigabits per second (Gbps). The predetermined operating rates of conventional transceiver circuitry typically limit the transceiver's ability to cover the entire operating range of the HDMI standard. Therefore, transceiver circuitry that operates at predetermined data rates can only support those HDMI standards having similar data rates to the transceiver circuitry.
In some instances, transceiver circuitry in an ASIC device leverages a phase-locked loop (PLL) circuit that has a voltage controlled oscillator (VCO) with a wide tuning range to support HDMI interfaces at different data rates (or other input-output standards with arbitrary data rates). This allows the ASIC device to meet the requirements of different HDMI applications. However, such a solution is generally undesirably costly.
As performance requirements increase and higher resolutions are introduced, transceiver circuitry may need to be adapted to support different input-output interfaces with different data rates. It is within this context that the embodiments described herein arise.